Á¦Ç°¼Ò°³
¤ýÀÚ¼¼ÃøÁ¤ÀåÄ¡, IMU, GPS/INS
¤ý°í¼º´É MEMS °ü¼º ¼¾¼­, ½Ã½ºÅÛ ¹× ÅëÇÕ GPS
¤ý°íÃâ·Â ¹«¼± ÁõÆø±â
¤ýGNSS ½Ã¹Ä·¹ÀÌÅÍ, GNSS Test & Software Receiver
¤ýIP Core Á¦Ç°
Cable
Codecs
 
- 802.16 Phy FEC
- J83 A,B,C and DVB-C
- Reed-Solomon
- Viterbi encoder decoders
Terrestrial
Satellite
General
¤ýÅë½ÅÄÉÀ̺í Æ÷¼³Àåºñ
¤ý½Ç³» À§Ä¡(ÃøÀ§) ÃßÀû ½Ã½ºÅÛ
¤ý¹«¼± µ¥ÀÌÅÍ Àü¼Û ½Ã½ºÅÛ
¤ý¼ö¼Ò ¸ÞÀÌÀú, ¼ö¼Ò ½Ã°è
¤ýGPS ½Ã°¢µ¿±âÈ­ Àåºñ
¤ýÃÊÁ¤¹Ð ½Ã°£ ÁÖÆļö Àåºñ
¤ý´ÙÁ߸ðµå¿ë Telemetry ¼Û/¼ö½Å±â
¤ýFilter Connector
  Global Partners
Exclusive Representative Contract
with Global Companies
IP Core Á¦Ç° > Codecs > Viterbi encoder decoders
 

Viterbi decoder (burst-mode),
Viterbi decoder (tail-biting)

Product codes: CMS0002, CMS0008

Our zero-terminated burst-mode Viterbi decoder (CMS0002) was designed specifically for block-based standards such as 802.11a and 802.16, but it is also suitable for a wide range of continuous-mode applications including DOCSIS (J.83-B) and DVB-T.
We also offer a tail-biting Viterbi decoder (CMS0008) which provides bandwidth-efficient Forward Error Correction in either continuous or discontinuous data transmission systems.


Block diagram



Click on image for further information


Downloads

Technical data brief, 8th May 2007 (119 kB)- Viterbi decoder (burst-mode)
Technical data brief, 8th May 2007 (110 kB)- Viterbi decoder (tail-biting)

E-mail me when these downloads are updated

Features of burst-mode

  • Native 1/2 coderate with user puncture.
  • Programmable constraint length.
  • Programmable generator coefficients.
  • Configurable traceback length.
  • Zero-flush mode for 802.11a, 802.16.
  • Minimum latency between code blocks.
  • Variable / arbitrary block size.
  • Significantly reduced group delay.

  • Features of tail-biting

  • Native 1/2 coderate with user puncture.
  • Programmable constraint length.
  • Programmable generator coefficients.
  • Zero latency between code blocks.
  • Fixed code block size.
  • Coding gain and group delay comparable to typical continuous-mode designs.

  • Implementation

  • Optimised for ASIC, Xilinx and Altera.
  •